This invention relates generally to methods and circuit configurations for measuring signal propagation delays, and in particular for measuring signal propagation delays through synchronous memory elements.
Integrated circuits (ICs) are the cornerstones of myriad computational systems, such as personal computers and communications networks. Purchasers of such systems have come to expect significant improvements in speed performance over time. The demand for speed encourages system designers to select ICs that guarantee superior speed performance. This leads IC manufactures to carefully test the speed performance of their designs.
FIG. 1 depicts a conventional test configuration 100 for determining the signal propagation delay of a test circuit 110 in a conventional IC 115. A tester 120 includes an output lead 125 connected to an input pin 130 of IC 115. Tester 120 also includes an input line 135 connected to an output pin 140 of IC 115.
Tester 120 applies an input signal to input pin 130 and measures how long the signal takes to propagate through test circuit 110 from input pin 130 to output pin 140. The resulting time period is the timing parameter for test circuit 110, the path of interest. Such parameters are typically published in literature associated with particular ICs and/or used to model the speed performance of circuit designs that employ the path of interest.
Conventional test procedures are problematic for at least two reasons. First, many signal paths within a given IC are not directly accessible via input and output pins, and therefore cannot be measured directly. Second, testers have tolerances that can have a significant impact on some measurements, particularly when the path of interest is relatively short. For example, if a tester accurate to one nanosecond measures a propagation delay of one nanosecond, the actual propagation delay might be any time between zero and two nanoseconds. In such a case the IC manufacturer would have to assume the timing parameter was two nanoseconds, the worst-case scenario. If ICs are not assigned worst-case values, some designs will fail. Thus, IC manufacturers tend to add relatively large margins of error, or xe2x80x9cguard bands,xe2x80x9d to ensure that their circuits will perform as advertised. Unfortunately, this means that those manufacturers will not be able to advertise their full speed performance, which could cost them customers in an industry where speed performance is paramount.
Programmable logic devices (PLDS) are a well-known type of digital integrated circuit that may be programmed by a user (e.g., a circuit designer) to perform specified logic functions. One type of PLD, the field-programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBS) that are programmably interconnected to each other and to programmable input/output blocks (IOBs). This collection of logic is configured by loading configuration data into internal configuration memory cells that define how the CLBS, interconnections, and IOBs are configured.
Each programming point, CLB, interconnection line, and IOB introduces some delay into a signal path. The many potential combinations of delay-inducing elements make timing predictions particularly difficult. FPGA designers use xe2x80x9cspeed filesxe2x80x9d that include resistance and capacitance values for the various delay-inducing elements and combine them to establish delays for desired signal paths. These delays are then used to predict circuit timing for selected circuit designs implemented as FPGA configurations. FPGA timing parameters are assigned worst-case values to ensure FPGA designs work as indicated.
Manufacturers of ICs, including FPGAS, would like to achieve the highest speed performance possible without causing ICs to fail to meet the guaranteed timing specifications. More accurate measurements of circuit timing allow IC designers to use smaller guard bands to ensure correct device performance, and therefore to guarantee higher speed performance. There is therefore a need for a more accurate means of characterizing IC speed performance.
The present invention provides an accurate means of measuring IC speed performance. The inventive circuit is particularly useful for testing programmable logic devices, which can be programmed to include a device for testing a majority of the requisite test circuitry.
The time required for the output of a memory cell, such as a flip-flop or random-access memory (RAM) cell, to store data in response to a clock signal is a parameter of interest in modeling IC speed performance. In accordance with one embodiment of the invention, a number of memory cells are configured in series. Each cell is initialized to store a known logic level, a voltage level representative of a logic zero for example. In an embodiment in which the cells are initialized to store logic zeroes, the first memory cell is clocked so that the output of the cell changes to a level representative of a logic one. The rising edge associated with the transition of the output from zero to one then clocks a subsequent memory cell, causing the output of the second memory cell to transition from zero to one. This sequence of events continues from one memory cell to the next so that the rising edge propagates through all of the memory cells in the series.
Because the memory cells are clocked in sequence, the time required for a rising edge to traverse the entire series of memory cells is the sum of the delays associated with writing logic one data into each of the individual memory cells. Consequently, the delay through the series of memory cells can be used to determine the clock-to-out delays associated with the memory cells. In one embodiment, the memory cells are arranged in a ring so that the series of memory cells forms a ring oscillator. In that embodiment, an initial clock edge traverses the series of memory cells and is then fed back to the first memory cell to traverse the series again. The oscillator is equipped with feedback circuitry that returns each memory cell to the initialized state before the return of the clock edge so that the individual cells are prepared to change state upon the receipt of each subsequent rising edge. Thus, the delay through the series depends upon only one type of write operation (e.g. writing logic ones). Circuits in accordance with the invention thus allow for independent measurements of the clock-to-out delays associated with writing logic ones and logic zeroes.
One embodiment of the invention includes a ring of synchronous memory cells that includes at least one RAM cell. A synchronous output terminal of the RAM cell connects only to the subsequent memory cell, which is to say that the RAM cell has a fanout of one. Reducing the fanout to one improves the measurement of clock-to-out delay by removing some of the delay associated with driving additional devices. Some such embodiments include a second memory cell for each memory cell connected in series. The output of the second memory cell resets the series-connected memory cell, preparing the series-connected memory cell to receive a subsequent clock edge.
This summary does not limit the invention, which is defined instead by the claims.